1. Field of the Invention
The present invention is related to an improved programmable cell for use in programmable electronic arrays such as PROM devices, logic arrays, gate arrays and die interconnect arrays. In particular each cell has a memory region made of a phase change material which is settable and non-resettable in a highly conductive state from a highly non-conductive state. This invention is related to the storing of information with phase change switch devices first invented by Stanford R. Ovshinsky, as for example, as disclosed in U.S. Pat. No. 3,271,591.
2. Description of the Prior Art
Heretofore various memory systems have been proposed which are divided into several types. One type is the serial type where the information in the memory system is obtained serially and where the read time for reading a particular bit of information in the memory is dependent upon where it is located in the memory. This results in long read times for obtaining the information from memory. Such types of memory systems include memory devices including a magnetic tape or a magnetic disc including the so-called floppy disc and magnetic "bubble memory" devices.
Another type of memory system is the random access memory system (RAM) where the read time for each bit is substantially the same as for any other bit.
While the storage information in "bubble" type memory devices potentially reduces the size and cost of memory systems and provides high information packing densities, i.e., small center-to-center distance between adjacent memory regions where the bits of information are stored, such "bubble" systems are limited to serial reading of information and do not provide for fast read, random access to the stored information.
Also, heretofore, short term data storage has been provided by RAM memory devices including transistors or capacitors at the cross over points of X and Y axis conductors. Such a memory device can be set in one of two operational states. These memory devices provide a fairly high packing density, i.e., a small center-to-center distance between memory locations. A major disadvantage is that such devices are volatile since they must be continually supplied with a voltage if they are to retain their stored data. Such short term data storage devices are often referred to as volatile fast read and write memory systems.
A fast read memory system is the read only memories (ROM) which use transistors and rectifiers formed in semiconductor substrates with permanently open contact points or permanently closed contact points for storage of bits of information. Such a ROM system is programmed during the manufacture thereof and has a short read time and a relatively high packing density as well as being non-volatile. However, the obvious disadvantage of such a ROM system is that the data stored cannot be altered in the field. Accordingly, ROM devices are made-to-order for applications involving storing of the basic operating program of a data processor or other user non-altered information.
Another memory system used is a programmable read only memory (PROM) system which can be programmed once by the user and remains in that state. Once it is programmed a PROM system will operate identically to a ROM system of the same configuration.
The most commonly used PROM system incorporates fuse links positioned at each cross over point of an X-Y matrix of conductors. The storage of information (logic one or logic zero) is obtained by blowing the fuse links in a given predetermined pattern. Such fuse links extend laterally on a substrate instead of vertically between cross over conductors and, as a result, such fuse links necessarily require a large area. The area of a typical memory cell or region utilizing a fuse link is about 1 to 1.6 mil.sup.2 (1 mil=0.001 inch).
The current needed to blow the fuse link for programming is quite high because of the necessity of completely blowing out the fuse link and because of the inherently high conductivity of the material of the fuse link. Typical currents are 50 milliamps and the power required is approximately 250 to 400 milliwatts. Also, the fuse link which is a narrow portion of a conductor deposited on a substrate, must have a precise dimension to ensure the complete and programmable blow out thereof. In this respect, photolithography and etching techniques required to fabricate such a fuse link require that such a fuse link be made with very critical tolerances in width, length and thickness.
Another major problem with fuse link type PROM devices is that the small gap in the blown fuse can become closed with accumulation of conductive material remaining adjacent to the gap by diffusion or otherwise.
The fuse link technology also has been utilized in field programmable logic arrays, gate arrays and die interconnect arrays. These arrays are utilized to provide options for the integrated circuit user between the standard high volume, low cost logic arrays and the very expensive handcrafted custom designed integrated circuits. These arrays allow a user to program the low cost array for the user's specific application at a substantially reduced cost from the cost of a custom application circuit.
One type of PROM switching element is shown in U.S. Pat. No. 4,146,902 in the name of Tanimoto. This patent illustrates a polycrystalline silicon resistor. The polycrystalline resistor is formed by high temperature, about 700.degree. C., chemical vapor deposition (CVD) process. There are several apparent disadvantages to such a process and the resulting resistors. First, if a platinum silicide diode is utilized, the processing of the resistor at 700.degree. C. potentially will destroy or seriously damage the platinum diode. Secondly, by its very nature, a polycrystalline structure has numerous and varied grain boundaries and other defects. This results in a wide distribution in switching levels, since each resistor will have different gain boundaries and defects and hence different switching characteristics. Thirdly, the polysilicon structure inherently is more conductive than an amorphous alloy and hence will be too conductive to be utilized with MOS devices which cannot withstand high current levels. The higher conductivity of the polycrystalline resistor also results in a relatively narrow range of doping and hence resistivity, so that the resistor switching parameters are not as flexible as desired.
Heretofore it has also been proposed to provide an EEPROM (electrically erasible programmable read only memory) device, a vertically disposed memory region or cell in a memory circuit which is vertically coupled at and between an upper Y axis conductor and a lower X axis conductor in a memory matrix. Such an EEPROM system provides a relatively high packing density. Examples of such EEPROM's are disclosed in U.S. Pat. No. 3,699,543 to Neale directed to: COMBINATION FILM DEPOSITED SWITCH UNIT AND INTEGRATED CIRCUIT and U.S. Pat. No. 4,177,475 to Holmberg directed to: HIGH TEMPERATURE AMORPHOUS MEMORY DEVICE FOR AN ELECTRICALLY ALTERABLE READ ONLY MEMORY.
These references illustrate EEPROM devices including a matrix of X and Y axis conductors where a memory circuit, including a memory region and an isolating device is located at each cross over point and extends generally perpendicularly to the cross over conductors thereby to provide a relatively high packing density.
The memory region utilized in such EEPROM devices have typically been formed of a tellurium-based chalcogenide material and more specifically an amorphous material such as amorphous germanium and tellurium. Other materials which have rather highly reversible memory regions include a Ge.sub.a Te.sub.b wherein a is between 5 and 70 atomic percent and b is between 30 and 95 atomic percent. Some of these materials also include other elements in various percentages from 0 to 40 in atomic percent such as antimony, bismuth, arsenic, sulfur and/or selenium.
Amorphous materials of the type described above have good reversibility and have sufficient thermal stability such that they will not deteriorate under the usual temperature conditions, in which they are utilized. The crystalline state is reset into its amorphous state by a high resetting current.
A preferred EEPROM material has (a) good reversibility of up to or greater than 10.sup.6 cycles, (b) a maximum processing temperature of about 200.degree. C., (c) a maximum storage temperature of about 100.degree. C., (d) a threshold voltage of 8 volts, (e) a SET resistance of 300 ohms and (f) an OFF resistance (at 175.degree. C.) of at least approximately 10.sup.4 ohms.
Heretofore it has also been known to provide isolating devices which are coupled in series with a memory region or cell between the cross over conductors, such isolating devices typically having been formed by diffusing various dopant materials into a single crystal silicon substrate to form a rectifier, transistor, or MOS device, e.g., a field effect transistor. Such a diffusion process results in lateral diffusion of the doped material into the substrate material and as a result the cell packing densities of such prior memory systems have been limited by the degree of lateral diffusion of the dopant materials and by the margin of error required for mask alignment.
Heretofore an all thin film EEPROM device has been proposed and is disclosed in U.S. Pat. No. 3,629,863 referred to above. The all film memory circuit disclosed in U.S. Pat. No. 3,629,863 utilizes deposited film bidirectional threshold type isolating devices.
The devices herein utilize for each isolating device a unidirectional isolating device like a rectifier or transistor which provides isolation by a high impedance P-N junction in one direction of current flow thereby to provide very high OFF resistance.
It has been proposed to form a P-N junction by vacuum depositing, either an N or P type amorphous semiconductor film on an oppositely doped silicon chip substrate. In this respect, reference is made to U.S. Pat. No. 4,062,034 which discloses such a thin film transistor having a P-N junction. It has not been proposed to use such a thin film deposited amorphous semiconductor film for forming an isolating device in a memory circuit which also includes a memory region in a programmable array.
Also, it has been previously proposed in parent application Ser. No. 201,594, to utilize an amorphous alloy which includes silicon and fluorine and which may also contain hydrogen to provide a thin film rectifier or transistor in the memory circuits of a programmable array. It also has heretofore been proposed to utilize silicon and fluorine materials in a solar cell which is essentially a photosensitive rectifier. In this respect, reference is made to the disclosure in U.S. Pat. No. 4,217,374, Stanford R. Ovshinsky and Masatsugu Izu entitled: AMORPHOUS SEMICONDUCTORS EQUIVALENT TO CRYSTALLINE SEMICONDUCTORS and U.S. Pat. No. 4,226,898, Stanford R. Ovshinsky and Arun Madan, of the same title.